Fawkes API
Fawkes Development Version
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00001 00002 /*************************************************************************** 00003 * mmx.h - MMX CPU extension support 00004 * 00005 * Copyright 1997-2001 H. Dietz and R. Fisher (copied form FFmpeg) 00006 * 00007 ****************************************************************************/ 00008 00009 /* This program is free software; you can redistribute it and/or modify 00010 * it under the terms of the GNU General Public License as published by 00011 * the Free Software Foundation; either version 2 of the License, or 00012 * (at your option) any later version. 00013 * 00014 * This program is distributed in the hope that it will be useful, 00015 * but WITHOUT ANY WARRANTY; without even the implied warranty of 00016 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00017 * GNU Library General Public License for more details. 00018 * 00019 * Read the full text in the LICENSE.GPL file in the doc directory. 00020 */ 00021 00022 #ifndef __FIREVISION_FVUTILS_CPU_MMX_H_ 00023 #define __FIREVISION_FVUTILS_CPU_MMX_H_ 00024 00025 namespace firevision { 00026 #if 0 /* just to make Emacs auto-indent happy */ 00027 } 00028 #endif 00029 00030 /// @cond MMX 00031 00032 /* 00033 * The type of an value that fits in an MMX register (note that long 00034 * long constant values MUST be suffixed by LL and unsigned long long 00035 * values by ULL, lest they be truncated by the compiler) 00036 */ 00037 00038 typedef union { 00039 long long q; /* Quadword (64-bit) value */ 00040 unsigned long long uq; /* Unsigned Quadword */ 00041 int d[2]; /* 2 Doubleword (32-bit) values */ 00042 unsigned int ud[2]; /* 2 Unsigned Doubleword */ 00043 short w[4]; /* 4 Word (16-bit) values */ 00044 unsigned short uw[4]; /* 4 Unsigned Word */ 00045 char b[8]; /* 8 Byte (8-bit) values */ 00046 unsigned char ub[8]; /* 8 Unsigned Byte */ 00047 float s[2]; /* Single-precision (32-bit) value */ 00048 } mmx_t; /* On an 8-byte (64-bit) boundary */ 00049 00050 00051 #define mmx_i2r(op,imm,reg) \ 00052 __asm__ __volatile__ (#op " %0, %%" #reg \ 00053 : /* nothing */ \ 00054 : "i" (imm) ) 00055 00056 #define mmx_m2r(op,mem,reg) \ 00057 __asm__ __volatile__ (#op " %0, %%" #reg \ 00058 : /* nothing */ \ 00059 : "m" (mem)) 00060 00061 #define mmx_r2m(op,reg,mem) \ 00062 __asm__ __volatile__ (#op " %%" #reg ", %0" \ 00063 : "=m" (mem) \ 00064 : /* nothing */ ) 00065 00066 #define mmx_r2r(op,regs,regd) \ 00067 __asm__ __volatile__ (#op " %" #regs ", %" #regd) 00068 00069 00070 #define emms() __asm__ __volatile__ ("emms") 00071 00072 #define movd_m2r(var,reg) mmx_m2r (movd, var, reg) 00073 #define movd_r2m(reg,var) mmx_r2m (movd, reg, var) 00074 #define movd_r2r(regs,regd) mmx_r2r (movd, regs, regd) 00075 00076 #define movq_m2r(var,reg) mmx_m2r (movq, var, reg) 00077 #define movq_r2m(reg,var) mmx_r2m (movq, reg, var) 00078 #define movq_r2r(regs,regd) mmx_r2r (movq, regs, regd) 00079 00080 #define packssdw_m2r(var,reg) mmx_m2r (packssdw, var, reg) 00081 #define packssdw_r2r(regs,regd) mmx_r2r (packssdw, regs, regd) 00082 #define packsswb_m2r(var,reg) mmx_m2r (packsswb, var, reg) 00083 #define packsswb_r2r(regs,regd) mmx_r2r (packsswb, regs, regd) 00084 00085 #define packuswb_m2r(var,reg) mmx_m2r (packuswb, var, reg) 00086 #define packuswb_r2r(regs,regd) mmx_r2r (packuswb, regs, regd) 00087 00088 #define paddb_m2r(var,reg) mmx_m2r (paddb, var, reg) 00089 #define paddb_r2r(regs,regd) mmx_r2r (paddb, regs, regd) 00090 #define paddd_m2r(var,reg) mmx_m2r (paddd, var, reg) 00091 #define paddd_r2r(regs,regd) mmx_r2r (paddd, regs, regd) 00092 #define paddw_m2r(var,reg) mmx_m2r (paddw, var, reg) 00093 #define paddw_r2r(regs,regd) mmx_r2r (paddw, regs, regd) 00094 00095 #define paddsb_m2r(var,reg) mmx_m2r (paddsb, var, reg) 00096 #define paddsb_r2r(regs,regd) mmx_r2r (paddsb, regs, regd) 00097 #define paddsw_m2r(var,reg) mmx_m2r (paddsw, var, reg) 00098 #define paddsw_r2r(regs,regd) mmx_r2r (paddsw, regs, regd) 00099 00100 #define paddusb_m2r(var,reg) mmx_m2r (paddusb, var, reg) 00101 #define paddusb_r2r(regs,regd) mmx_r2r (paddusb, regs, regd) 00102 #define paddusw_m2r(var,reg) mmx_m2r (paddusw, var, reg) 00103 #define paddusw_r2r(regs,regd) mmx_r2r (paddusw, regs, regd) 00104 00105 #define pand_m2r(var,reg) mmx_m2r (pand, var, reg) 00106 #define pand_r2r(regs,regd) mmx_r2r (pand, regs, regd) 00107 00108 #define pandn_m2r(var,reg) mmx_m2r (pandn, var, reg) 00109 #define pandn_r2r(regs,regd) mmx_r2r (pandn, regs, regd) 00110 00111 #define pcmpeqb_m2r(var,reg) mmx_m2r (pcmpeqb, var, reg) 00112 #define pcmpeqb_r2r(regs,regd) mmx_r2r (pcmpeqb, regs, regd) 00113 #define pcmpeqd_m2r(var,reg) mmx_m2r (pcmpeqd, var, reg) 00114 #define pcmpeqd_r2r(regs,regd) mmx_r2r (pcmpeqd, regs, regd) 00115 #define pcmpeqw_m2r(var,reg) mmx_m2r (pcmpeqw, var, reg) 00116 #define pcmpeqw_r2r(regs,regd) mmx_r2r (pcmpeqw, regs, regd) 00117 00118 #define pcmpgtb_m2r(var,reg) mmx_m2r (pcmpgtb, var, reg) 00119 #define pcmpgtb_r2r(regs,regd) mmx_r2r (pcmpgtb, regs, regd) 00120 #define pcmpgtd_m2r(var,reg) mmx_m2r (pcmpgtd, var, reg) 00121 #define pcmpgtd_r2r(regs,regd) mmx_r2r (pcmpgtd, regs, regd) 00122 #define pcmpgtw_m2r(var,reg) mmx_m2r (pcmpgtw, var, reg) 00123 #define pcmpgtw_r2r(regs,regd) mmx_r2r (pcmpgtw, regs, regd) 00124 00125 #define pmaddwd_m2r(var,reg) mmx_m2r (pmaddwd, var, reg) 00126 #define pmaddwd_r2r(regs,regd) mmx_r2r (pmaddwd, regs, regd) 00127 00128 #define pmulhw_m2r(var,reg) mmx_m2r (pmulhw, var, reg) 00129 #define pmulhw_r2r(regs,regd) mmx_r2r (pmulhw, regs, regd) 00130 00131 #define pmullw_m2r(var,reg) mmx_m2r (pmullw, var, reg) 00132 #define pmullw_r2r(regs,regd) mmx_r2r (pmullw, regs, regd) 00133 00134 #define por_m2r(var,reg) mmx_m2r (por, var, reg) 00135 #define por_r2r(regs,regd) mmx_r2r (por, regs, regd) 00136 00137 #define pslld_i2r(imm,reg) mmx_i2r (pslld, imm, reg) 00138 #define pslld_m2r(var,reg) mmx_m2r (pslld, var, reg) 00139 #define pslld_r2r(regs,regd) mmx_r2r (pslld, regs, regd) 00140 #define psllq_i2r(imm,reg) mmx_i2r (psllq, imm, reg) 00141 #define psllq_m2r(var,reg) mmx_m2r (psllq, var, reg) 00142 #define psllq_r2r(regs,regd) mmx_r2r (psllq, regs, regd) 00143 #define psllw_i2r(imm,reg) mmx_i2r (psllw, imm, reg) 00144 #define psllw_m2r(var,reg) mmx_m2r (psllw, var, reg) 00145 #define psllw_r2r(regs,regd) mmx_r2r (psllw, regs, regd) 00146 00147 #define psrad_i2r(imm,reg) mmx_i2r (psrad, imm, reg) 00148 #define psrad_m2r(var,reg) mmx_m2r (psrad, var, reg) 00149 #define psrad_r2r(regs,regd) mmx_r2r (psrad, regs, regd) 00150 #define psraw_i2r(imm,reg) mmx_i2r (psraw, imm, reg) 00151 #define psraw_m2r(var,reg) mmx_m2r (psraw, var, reg) 00152 #define psraw_r2r(regs,regd) mmx_r2r (psraw, regs, regd) 00153 00154 #define psrld_i2r(imm,reg) mmx_i2r (psrld, imm, reg) 00155 #define psrld_m2r(var,reg) mmx_m2r (psrld, var, reg) 00156 #define psrld_r2r(regs,regd) mmx_r2r (psrld, regs, regd) 00157 #define psrlq_i2r(imm,reg) mmx_i2r (psrlq, imm, reg) 00158 #define psrlq_m2r(var,reg) mmx_m2r (psrlq, var, reg) 00159 #define psrlq_r2r(regs,regd) mmx_r2r (psrlq, regs, regd) 00160 #define psrlw_i2r(imm,reg) mmx_i2r (psrlw, imm, reg) 00161 #define psrlw_m2r(var,reg) mmx_m2r (psrlw, var, reg) 00162 #define psrlw_r2r(regs,regd) mmx_r2r (psrlw, regs, regd) 00163 00164 #define psubb_m2r(var,reg) mmx_m2r (psubb, var, reg) 00165 #define psubb_r2r(regs,regd) mmx_r2r (psubb, regs, regd) 00166 #define psubd_m2r(var,reg) mmx_m2r (psubd, var, reg) 00167 #define psubd_r2r(regs,regd) mmx_r2r (psubd, regs, regd) 00168 #define psubw_m2r(var,reg) mmx_m2r (psubw, var, reg) 00169 #define psubw_r2r(regs,regd) mmx_r2r (psubw, regs, regd) 00170 00171 #define psubsb_m2r(var,reg) mmx_m2r (psubsb, var, reg) 00172 #define psubsb_r2r(regs,regd) mmx_r2r (psubsb, regs, regd) 00173 #define psubsw_m2r(var,reg) mmx_m2r (psubsw, var, reg) 00174 #define psubsw_r2r(regs,regd) mmx_r2r (psubsw, regs, regd) 00175 00176 #define psubusb_m2r(var,reg) mmx_m2r (psubusb, var, reg) 00177 #define psubusb_r2r(regs,regd) mmx_r2r (psubusb, regs, regd) 00178 #define psubusw_m2r(var,reg) mmx_m2r (psubusw, var, reg) 00179 #define psubusw_r2r(regs,regd) mmx_r2r (psubusw, regs, regd) 00180 00181 #define punpckhbw_m2r(var,reg) mmx_m2r (punpckhbw, var, reg) 00182 #define punpckhbw_r2r(regs,regd) mmx_r2r (punpckhbw, regs, regd) 00183 #define punpckhdq_m2r(var,reg) mmx_m2r (punpckhdq, var, reg) 00184 #define punpckhdq_r2r(regs,regd) mmx_r2r (punpckhdq, regs, regd) 00185 #define punpckhwd_m2r(var,reg) mmx_m2r (punpckhwd, var, reg) 00186 #define punpckhwd_r2r(regs,regd) mmx_r2r (punpckhwd, regs, regd) 00187 00188 #define punpcklbw_m2r(var,reg) mmx_m2r (punpcklbw, var, reg) 00189 #define punpcklbw_r2r(regs,regd) mmx_r2r (punpcklbw, regs, regd) 00190 #define punpckldq_m2r(var,reg) mmx_m2r (punpckldq, var, reg) 00191 #define punpckldq_r2r(regs,regd) mmx_r2r (punpckldq, regs, regd) 00192 #define punpcklwd_m2r(var,reg) mmx_m2r (punpcklwd, var, reg) 00193 #define punpcklwd_r2r(regs,regd) mmx_r2r (punpcklwd, regs, regd) 00194 00195 #define pxor_m2r(var,reg) mmx_m2r (pxor, var, reg) 00196 #define pxor_r2r(regs,regd) mmx_r2r (pxor, regs, regd) 00197 00198 00199 /* 3DNOW extensions */ 00200 00201 #define pavgusb_m2r(var,reg) mmx_m2r (pavgusb, var, reg) 00202 #define pavgusb_r2r(regs,regd) mmx_r2r (pavgusb, regs, regd) 00203 00204 00205 /* AMD MMX extensions - also available in intel SSE */ 00206 00207 00208 #define mmx_m2ri(op,mem,reg,imm) \ 00209 __asm__ __volatile__ (#op " %1, %0, %%" #reg \ 00210 : /* nothing */ \ 00211 : "m" (mem), "i" (imm)) 00212 #define mmx_r2ri(op,regs,regd,imm) \ 00213 __asm__ __volatile__ (#op " %0, %%" #regs ", %%" #regd \ 00214 : /* nothing */ \ 00215 : "i" (imm) ) 00216 00217 #define mmx_fetch(mem,hint) \ 00218 __asm__ __volatile__ ("prefetch" #hint " %0" \ 00219 : /* nothing */ \ 00220 : "m" (mem)) 00221 00222 00223 #define maskmovq(regs,maskreg) mmx_r2ri (maskmovq, regs, maskreg) 00224 00225 #define movntq_r2m(mmreg,var) mmx_r2m (movntq, mmreg, var) 00226 00227 #define pavgb_m2r(var,reg) mmx_m2r (pavgb, var, reg) 00228 #define pavgb_r2r(regs,regd) mmx_r2r (pavgb, regs, regd) 00229 #define pavgw_m2r(var,reg) mmx_m2r (pavgw, var, reg) 00230 #define pavgw_r2r(regs,regd) mmx_r2r (pavgw, regs, regd) 00231 00232 #define pextrw_r2r(mmreg,reg,imm) mmx_r2ri (pextrw, mmreg, reg, imm) 00233 00234 #define pinsrw_r2r(reg,mmreg,imm) mmx_r2ri (pinsrw, reg, mmreg, imm) 00235 00236 #define pmaxsw_m2r(var,reg) mmx_m2r (pmaxsw, var, reg) 00237 #define pmaxsw_r2r(regs,regd) mmx_r2r (pmaxsw, regs, regd) 00238 00239 #define pmaxub_m2r(var,reg) mmx_m2r (pmaxub, var, reg) 00240 #define pmaxub_r2r(regs,regd) mmx_r2r (pmaxub, regs, regd) 00241 00242 #define pminsw_m2r(var,reg) mmx_m2r (pminsw, var, reg) 00243 #define pminsw_r2r(regs,regd) mmx_r2r (pminsw, regs, regd) 00244 00245 #define pminub_m2r(var,reg) mmx_m2r (pminub, var, reg) 00246 #define pminub_r2r(regs,regd) mmx_r2r (pminub, regs, regd) 00247 00248 #define pmovmskb(mmreg,reg) \ 00249 __asm__ __volatile__ ("movmskps %" #mmreg ", %" #reg) 00250 00251 #define pmulhuw_m2r(var,reg) mmx_m2r (pmulhuw, var, reg) 00252 #define pmulhuw_r2r(regs,regd) mmx_r2r (pmulhuw, regs, regd) 00253 00254 #define prefetcht0(mem) mmx_fetch (mem, t0) 00255 #define prefetcht1(mem) mmx_fetch (mem, t1) 00256 #define prefetcht2(mem) mmx_fetch (mem, t2) 00257 #define prefetchnta(mem) mmx_fetch (mem, nta) 00258 00259 #define psadbw_m2r(var,reg) mmx_m2r (psadbw, var, reg) 00260 #define psadbw_r2r(regs,regd) mmx_r2r (psadbw, regs, regd) 00261 00262 #define pshufw_m2r(var,reg,imm) mmx_m2ri(pshufw, var, reg, imm) 00263 #define pshufw_r2r(regs,regd,imm) mmx_r2ri(pshufw, regs, regd, imm) 00264 00265 #define sfence() __asm__ __volatile__ ("sfence\n\t") 00266 00267 /* SSE2 */ 00268 #define pshufhw_m2r(var,reg,imm) mmx_m2ri(pshufhw, var, reg, imm) 00269 #define pshufhw_r2r(regs,regd,imm) mmx_r2ri(pshufhw, regs, regd, imm) 00270 #define pshuflw_m2r(var,reg,imm) mmx_m2ri(pshuflw, var, reg, imm) 00271 #define pshuflw_r2r(regs,regd,imm) mmx_r2ri(pshuflw, regs, regd, imm) 00272 00273 #define pshufd_r2r(regs,regd,imm) mmx_r2ri(pshufd, regs, regd, imm) 00274 00275 #define movdqa_m2r(var,reg) mmx_m2r (movdqa, var, reg) 00276 #define movdqa_r2m(reg,var) mmx_r2m (movdqa, reg, var) 00277 #define movdqa_r2r(regs,regd) mmx_r2r (movdqa, regs, regd) 00278 #define movdqu_m2r(var,reg) mmx_m2r (movdqu, var, reg) 00279 #define movdqu_r2m(reg,var) mmx_r2m (movdqu, reg, var) 00280 #define movdqu_r2r(regs,regd) mmx_r2r (movdqu, regs, regd) 00281 00282 #define pmullw_r2m(reg,var) mmx_r2m (pmullw, reg, var) 00283 00284 #define pslldq_i2r(imm,reg) mmx_i2r (pslldq, imm, reg) 00285 #define psrldq_i2r(imm,reg) mmx_i2r (psrldq, imm, reg) 00286 00287 #define punpcklqdq_r2r(regs,regd) mmx_r2r (punpcklqdq, regs, regd) 00288 #define punpckhqdq_r2r(regs,regd) mmx_r2r (punpckhqdq, regs, regd) 00289 00290 /// @endcond 00291 00292 } // end namespace firevision 00293 00294 #endif